1. Field of the Invention
The present invention relates generally to buffers, and more specifically to PECL buffers.
2. Description of the Prior Art
Many circuits and systems employ small voltage swings in order to speed up system operation and decrease power consumption. For instance, using CMOS voltage levels, a small voltage swing from 3.9 volts to 1.2 volts may be accomplished much more quickly than a larger swing from 5 volts to 0 volts. A system or circuit employing a single-ended voltage swing, as opposed to a differential pair voltage swing, may be very fast but lack needed signal drive. For this reason, a differential pair buffer may be used to convert the single-ended signal to a differential signal pair in order to boost the drive, thereby obtaining even faster system or circuit operation. A PECL signal pair is thus required in applications where a high speed clock rate or data rate is necessary. The PECL signal pair is usually a differential signal pair with a small voltage signal swing between two positive signals. For example, if the power supply is 5 volts, the PECL signal may swing from 3.9 volts to 1.2 volts.
Usually BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) buffers are used to achieve a small differential voltage swing of high speed data or clock signals, with a differential clock or data signal pair known as PECL (Pseudo Emitter Common Logic) signals, but the costs associated with BiCMOS buffers at high frequencies are well known in the art. Thus, CMOS or NMOS technology is attractive as an alternative to BiCMOS technology, because CMOS or NMOS technology may be directly connected to the differential clock or data signal pair thereby further increasing system or circuit operation. For example, in the frequency range of approximately 150 MHz and greater, a CMOS process provides cost effectiveness and is often used.
In converting a single-ended signal to a differential signal pair, it is important that the differential signals be matched in terms of phase, or signal integrity will suffer. If the differential signals are out of phase, skew is introduced to the system causing the system speed to suffer. The transistor threshold voltage, V.sub.T, of CMOS or NMOS transistors can affect the duty cycle of the PECL differential pair buffer and thus has a direct impact on the amount of skew that exists between the PECL differential pair. When the input voltage is swinging from a first voltage to a second voltage, for instance, the differential pair signal is not continuous until the input voltage rises above the threshold voltage V.sub.T of the transistor. In this way, skew occurs between the differential pair.
It is important that the PECL output buffer differential signal pair be matched in terms of phase so that signal skew is minimized and high speed operation is accomplished. For instance, consider a 166 MHz system having a 6 nS period. In a 50% duty cycle, 3 nS is allocated to the high portion of the cycle while 3 nS is allocated to the low portion of the cycle. If 1 nS is required for both rise and fall times, the signal is effectively available for only 1 nS. Thus, skew can not exceed 1 nS or there will be no differential pair signal at all. Furthermore, any skew will degrade the integrity of the PECL output buffer differential pair and slow down the differential signal pair. The 50% duty cycle is an example; the duty cycle of the incoming signal may or may not be equal to 50%.
Thus, there is an unmet need in the art to minimize, and preferably eliminate, phase mismatch between signals of a differential pair derived from an single-ended input signal such that skew is minimized and thus signal speed may be maximized. Reducing or eliminating skew between the differential signal pair will enable the circuit or system to achieve a higher speed of operation.